ZX-Badaloc Reloaded
A Spartan-3E FPGA implementation of the ZX-Badaloc Spectrum clone
Loading Space Raiders on the Xilinx 3E board
This project is aimed at synthesizing the ZX-Badaloc, an enhanced ZX-Spectrum Clone developed in Italy, into a Xilinx SPARTAN-3E Fpga. The original project's main CPLD, I/O and Keyboard cplds, Z80 Processor, IDT dualport video ram can be squeezed into a single chip. This solves the main problem: WIRINGS !
Top and bottom views of the original clone, made in 2006
The new project has been developed by the same author and runs on the Xilinx Spartan 3E evaluation board HW-SPAR3E-SK-UNI-G featuring an XC3S500E fpga (see pictures of my board here).A small modification is required to improve the 8-color VGA output, but the board can run the clone AS IT IS, just missing the brightness control on ZX-Spectrum screen. Once uploaded to the FPGA via Jtag or the usb cable provided in the kit, Z80 firmware (the system bootrom and Sinclair ROMs or whatever) can be flashed on the onboard nonvolatile memory using the Z80 itself, in conjunction with the ZX-Com program (see the quickstart instructions).
The main processor is the opencores T80.
The project also includes a PicoBlaze processor which handles the LCD display, the Encoder knob, some of the switch/buttons and leds. Z80 speed can be adjusted on-the-fly by turning the encoder knob from 42MHz down to one instruction every two seconds with single step capability, with address and opcodes displayed on the LCD.
A running point on the LED bar shows the real Z80 execution speed and completes a turn (8 steps) every 500.000 opcode fetch. The result is affected by Z80 clock speed, type of instructions being executed, speed of memory, speed of I/O devices.
Current version can now run ResiDOS by Garry Lancaster.
Download Page: Here you will find all the files needed to run the clone.
StartUp instructions: step by step explanation about how to run the project on your board
Implemented I/O register list, available to T80
Latest Updates:
28/02/2009
FPGA V1.32b: The prescaler's
slowdown takes now (properly) place from the very first step of the encoder
setting.
ZX-Com
V5.2b: RS-232 buffers enlarged so that a full 64K (65536 bytes) block can be
transferred in one shot. The Flash --> Get Rom Bank command works now on
badaloc_nano too.
17/02/2009
Corrected a mistake in the 'quickstart'
page about the RS-232 cable
14/01/2009
Bootrom Firmware
V0.99b: ResiDOS 2.08 signature correctly located in ddr memory so that the [R]
ResiDOS option is displayed on main menu'
PicoBlaze Firmware V1.13: FPGA
Breakpoint registers are now continuously updated, in case of FPGA reset (picoblaze
is insensitive to reset)
10/01/2009
ZX-Com V5.2: Bugfix: the
fastpage bank is now properly initialized with real hardware value when the
program connects to the clone.
$54DF, $64DF and zx-mmc+ $7F registers can now
be manually edited in the Snapshot Editor.
06/01/2009
FPGA V1.32: The breakpoint logic
reacts to any memory access and not only on opcode fetch (as before). For
example, this allow triggering on screen writes.
FPGA V1.31: Added an internal reset
generator based on a counter, to overcome the lack of a true external reset
signal. The counter is restarted by the button that was previously the reset
signal itself (BTN_NORTH). The reset is also held active until the main PLL is
stable (locked).
The NMI button (BTN_SOUTH) is no longer hard-wired to T80
NMI_n pin. PicoBlaze reads the button and handles T80 NMI signal through an I/O
port. This allows a good button debounce and let the picoblaze issue an NMI for
other reason (none by now).
PicoBlaze Firmware V1.12: T80 NMI handler added on
BTN_SOUTH.
Bootrom Firmware
V0.99: If an NMI is received while already servicing an NMI, then a
warm_restart is performed. The bootrom firmware main menu is entered without
reloading the DDR bank from SPI flash rom, saving time. This function required a
good NMI button debounce (handled by picoblaze).
NEW: The project is now also being developed for the small
Avnet 3A Evaluation Board as
